In designing the wiring of a printed circuit board, it has recently become common to provide design constraining conditions due to the decrease of the voltage of LSIs, the increase of the speed of the signal speed, etc. To match the timings of signals with each other that run in a wiring pattern interconnecting parts, there is a design constraining condition to instruct the line length for each wiring path such that each line length is acquired by a conversion based on a delay (propagation delay) of a signal running through the wiring path.
As to a group such as a bus including a plurality of wiring paths, a design constraining condition instructs equal delays such that input timings for receivers of the wiring paths coincide. A designing engineer executes the wiring work such that the design constraining condition is satisfied. However, a long time is needed for the work of wiring the wiring paths adjusting the line lengths thereof to comply with the constraints concerning the delays of the signals in the wiring paths without violating the design rules. Therefore, a wiring designing tool is disclosed that complies with the line length constraining condition (see, e.g., Japanese Laid-Open Patent Publication No. H11-110434).
However, in the conventional wiring designing tool, a display that presents non-complying line length of the wiring length is displayed in a window that is different from a screen that displays the wiring pattern. Therefore, a problem arises that it is difficult to cope with the correspondence of a wiring pattern to a non-complying line length. Another problem also arises that it is difficult to imagine an actual wiring pattern length that corresponds to a non-complying line length.